AHB Master:
Initiates Read and Write operations by providing an address and control information
AHB Slave :
Responds to a Read or Write operation within a given address-space range.
AHB Arbiter:
Allows to initiate data transfer(depending on master request)only one master will perform the transaction at a time.
AHB Decoder:
Decode the address of each transfer and provide a select signal for the slave that is involved in the transfer.
Subscribe to:
Post Comments (Atom)
Verilog Course Team is EDS for VLSI is being managed by Engineers/Professionals possesing significant industrial experience across various application domains and engineering horizontals.Our engineers have expertise across a wide range of technologies,to the engineering efforts of our clients.Leveraging standards based components and investments in dedicated test lab infrastructure,we offer innovative,flexible and cost-effective Services and Solutions.
No comments:
Post a Comment