AMBA-AHB

AMBA AHB Operation -Overview

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AMBA AHB transfer can start with the bus master,by asserting a request signal to the arbiter.Then the arbiter when the master will be granted to use the bus.A granted Master bus starts the transfer with address and control signals.The transfer should include the following details

Burst Size
Size
Write Data
Address
Write/Read Operation
Transaction Types

Every transfer consists of an address and control cycle.

Basic Terminology

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Bus Cycle:
Defined from rising -edge to rising edge of transitions.
Bus Transfer:
A Read or Write operation of a data objects ,which may take one or more cycles.

Burst Operations:
Defined as one or more data transactions, initiated by a bus master.

AMBA AHB System Basic components

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AHB Master:
Initiates Read and Write operations by providing an address and control information

AHB Slave :
Responds to a Read or Write operation within a given address-space range.

AHB Arbiter:
Allows to initiate data transfer(depending on master request)only one master will perform the transaction at a time.

AHB Decoder:
Decode the address of each transfer and provide a select signal for the slave that is involved in the transfer.

Introduction

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AMBA-Advanced Microcontroller Bus Architecture

Widely used as the on-chip bus for ARM processors.

Four Distinct Buses of AMBA,

Advanced eXtensible Interface (AXI)
Advanced High-performance Bus (AHB)
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)

AMBA-AHB Features

High Performance
Pipelined Operation
Multiple Bus Master
Split Transfer
Burst Transfer

AMBA-ASB Features

High Performance
Pipelined Operation
Multiple Bus Master

AMBA-APB Features

Low Power
Latched Address
Simple Interface
Suitable to many Peripherals